This invention relates to a semiconductor device wherein a plurality of semiconductor layers each formed with a semiconductor element or elements are stacked. More particularly, the invention is concerned with the technique of signal transmission between the semiconductor layers of such a semiconductor device.
The degree of integration in a semiconductor integrated circuit has in recent years been increased to a remarkable extent. Particularly, remarkable progress in the technique of minute fabrication has made it possible to easily form an element or wiring whose minimum dimension is approximately 1 .mu.m. Further, for the purpose of increasing the degree of integration, not only integration of semiconductor elements on one semiconductor substrate but also the development of what is called a "three dimensional IC", wherein the semiconductor layer formed with said elements is stacked two or more in number, has recently been made on a popular basis. One of the basic problems in connection with such a three-dimensional IC occurs with the signal transmission between the circuits respectively formed in different semiconductor layers. That is, many problems have arisen in connection with the formation of interconnection for transmitting a signal processed by a circuit formed in a semiconductor layer to a circuit formed in another semiconductor layer.
The problem having occurred with the above-mentioned prior art three-dimensional IC will now briefly be explained with reference to FIG. 1. FIG. 1 is a sectional view showing, in simplified form, the interconnections between the different semiconductor layers of a three-dimensional IC. In FIG. 1, the drain 12 of an MOS transistor formed in the n-th semiconductor layer 11 is electrically connected by a conductor 17 to the source 14 of an MOS transistor formed in the (n+1)th semiconductor layer 13. For example, data processed by a circuit in the n-th semiconductor layer 11 is selected by a selective gate 15 and is outputted from the drain 12. The data outputted is transmitted through the conductor 17 to the source 14 of the MOS transistor formed in the (n+1)th semiconductor layer. The signal, further, is selected by a selective gate 18 and outputted to enter a circuit formed in the semiconductor layer 13, in which it is subjected to signal processing.
In manufacturing the three-dimensional integrated circuit explained above, after the formation of the integrated circuit in the n-th semiconductor layer 11, for example, an intervening insulating film 16 consisting of SiO.sub.2 is first formed on the semiconductor layer 11 and a through hole is provided in the film 16. Thereafter, the conductor 17 consisting, for example, of a polycrystalline silicon doped with an impurity is filled into the through hole. Thereafter, the (n+1)th semiconductor layer 13 is formed on the intervening insulating film 16 and is formed with an integrated circuit including an MOS transistor. In this case, the source 14 of the MOS transistor thus formed in the (n+1)th semiconductor layer 13 is connected by a diffusion layer 19 to the conductor 17.
In the manufacture of the said three-dimensional integrated circuit, it is difficult to form with a high yield such a fine through hole and further it is also extremely difficult to successfully fill the conductive material into the through hole thus formed. The formation of such a conductor penetrating through the intervening insulating film 16 is particularly difficult for the reason that when, for example, the (n+1)th semiconductor layer 13 is formed by recrystallizing, for example, a polycrystalline semiconductor layer by subjecting the same to laser annealing, it is necessary to form the insulating film 16 to an appreciable great thickness (1.about.5 .mu.m) so as to prevent the heat generated due to the laser exposure from having an undesirable effect upon the elements formed in the n-th semiconductor layer 11. Further, for the purpose of preventing the conductor 17 from being deteriorated due to the laser exposure or having undesired reactions with the semiconductor layer 13, a limitation was imposed upon the selection of the material of the conductor 17. That is, the material of the conductor 17 was limited to a polycrystalline silicon, refractory metal or the like having heat resistance and having no reaction with silicon. These problems not only cause a decrease in the manufacturing yield of the three-dimensional IC but also become the causes of obstructing the increase or extension of the function thereof.
FIG. 2 shows an example of the prior art three-dimensional integrated circuit, which is a one chip computer consisting of five layers 21 to 25. The first layer 21 and the second layer 22 are each a RAM having a 1M bit capacity, the third layer 23 is a microprocessor for performing the signal processing, namely CPU (Central Processing Unit), the fourth layer 24 is a 4M bit ROM stored with a program, and the fifth layer 25 as the uppermost layer is a controller having, in addition to the function of controlling the signals supplied to the other layers, the functions of interfacing, performing the sequence processing, etc. To cause the one-chip computer having the above-mentioned construction to function effectively, it is necessary to permit a free transmission and reception of a signal between each of the layers. Particularly, the controller layer 25 is required to make its transmission and reception of a signal to and from each of the other layers at all times. In the three-dimensional IC having such prior art construction or structure, therefore, it is necessary to form a conductor connecting the fifth layer 25 and the first layer 21, that is, to form through holes and fill a conductive material into these through holes. Extreme difficulties are encountered, however, in meeting such a necessity. Further, since a signal is very often transmitted from one layer to another through the controller, a delay in the signal transmission becomes a great problem.